1. Technical Field
The present invention relates in general to a method and system for improved data transfer and in particular to a method and system for data transfer between a memory device and a processor. Still more particularly, the present invention relates to an improved method and system for reading from a m-byte memory device utilizing a processor having a n-byte data bus, where m is less than or equal to n.
2. Description of the Related Art
A personal computer system is a powerful and cost effective tool for data processing. Prevalent models of personal computers include the IBM PC/AT and the PS/2, both of which are built around either a 80386 or 80486 processor architecture. These personal computer system architectures are collectively designated x86. In order to support a wide variety of data processing functions and structures, x86 processors are often interfaced to devices having a broad range of bit widths, including 8-, 16-, and 32-bit memory devices. Since the cost of memory increases dramatically with increased bit width, it is particularly advantageous for manufacturers of personal computer system to utilize 8-bit memory devices in order to produce products that are price competitive.
The x86 processor architecture supports direct connection between a processor and 8-, 16-, or 32-bit memory devices. However, since an x86 processor has a 32-bit data bus, the processor must determine which bits present on the data bus are valid when the processor is interfaced with an 8- or 16-bit memory. The processor determines which bits on the data bus are valid by a process of dynamic bus sizing in which the processor samples two bus control pins (BS8 and BS16) each bus cycle to determine if a bus transaction is a transfer between the processor and an 8- or 16-bit device. The processor determines whether the transaction involves an 8- or 16-bit device by internally decoding signals BS8 and BS16. When either of the two bus control signals is asserted, the x86 processor must run additional bus cycles if the transaction is a data transfer of a larger number of bytes than the byte width of the memory device. For example, a 486 processor can ordinarily complete a read of a 32-bit value from a 32-bit memory in two bus cycles. However, if the 32-bit value must be read one byte at a time from an 8-bit memory, the read operation would require a minimum of 8 bus cycles.
The dynamic bus sizing feature functions differently in the 386 and 486 processors. When a 386 processor performs a 4-byte read from an 8-bit memory device, for example, the processor reads the 4 bytes on the lowest 8 bits of the data bus (D7-D0) during 4 successive read cycles (a read cycle requires a minimum of 2 bus cycles). In contrast, when a 486 performs a similar read operation, the most significant byte must be driven on data pins D31-D24, the next most significant byte on D23-D16, the third most significant byte on pins D15-D8, and the least significant byte on pins D7-D0. However, like the 386, the 486 processor will perform the 4-byte read in 4 successive read cycles on the bus.
One advance of the 486 over the 386 processor is that the 486 processor is capable of operating in a burst mode. During a burst cycle, data is read or written during every clock cycle rather than every other clock cycle as occurs in non-burst mode. Other than performing a read or write in a single bus cycle, burst mode reads and writes to 8 and 16-bit memories are executed the same as regular read and write operations. One important application of burst mode is to quickly fill the internal cache of the 486 processor.
In response to consumer demand for increased performance in personal computer systems, manufacturers have sought to increase processing speed through streamlining the instruction sets of processors and by developing processors capable of performing multiple instructions during a single clock cycle. The Reduced Instruction Set Computer (RISC) processor is one such device. Despite the enhanced processing performance available with a RISC processor, overall performance remains degraded when reading data from a device interfaced to the processor which has a bit width narrower than the RISC processor bus width.
Consequently, it would be desirable to have a method and system for transferring data between a 64-bit processor, such as the RISC processor, and an 8-bit memory device without requiring the processor to support extra bus cycles or additional internal decodes.